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  • Publish Date：2026-08-11
NSTC, NYCU, and TSMC Break Key Barrier in 2D Semiconductors
NYCU Joins Taiwan’s First High School–University–Research Alliance to Cultivate Future Scientists
Professor Wen-Hao Chang’s team at NYCU’s Department of Electrophysics has developed a high-performance monolayer molybdenum disulfide (MoS₂) top-gate transistor, addressing a longstanding interface challenge in two-dimensional semiconductors.
 
Edited by Chance Lai
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Researchers at National Yang Ming Chiao Tung University (NYCU), in collaboration with Taiwan Semiconductor Manufacturing Co. (TSMC) and Academia Sinica, with support from the National Science and Technology Council (NSTC), have cleared a major hurdle in the development of two-dimensional semiconductors.

The team created a high-performance top-gate transistor using a single layer of molybdenum disulfide (MoS₂). Despite its atom-scale dimensions, the device delivers high transconductance, extremely low leakage current and stable operation — a combination that has long proved difficult to achieve in 2D electronics. The findings were reported in Nature Electronics, marking an important step toward integrating 2D semiconductors into practical chip technologies.

Why Atom-Thin Semiconductors Matter

The collaboration brought together teams led by Professor Wen-Hao Chang of NYCU’s Department of Electrophysics and Academia Sinica’s Research Center for Applied Sciences, Dr. Iuliana P. Radu of TSMC, and Professor Tsung-En Lee of NYCU’s Department of Semiconductor Engineering. The project was supported by the NSTC’s Angstrom Semiconductor Initiative and the Taiwan Chip-based Industrial Innovation Program’s project on Key Technologies for Integrating Next-Generation Semiconductor Materials and Devices.

From smartphones and computers to the next generation of artificial intelligence devices, modern electronics require chips that can process more information while consuming less power. For decades, the semiconductor industry has achieved this goal by shrinking silicon transistors. But as conventional silicon technology approaches its physical limits, researchers worldwide are seeking new materials to continue advancing chip performance.

Two-dimensional semiconductors are among the most promising candidates. Because they can be as thin as a single atomic layer, they offer exceptional control over electrical current even at extremely small dimensions. That makes them a potential pathway to extend transistor scaling and sustain the progress associated with Moore’s law. But being extraordinarily thin also makes these materials highly sensitive.

To control the flow of current through a transistor, engineers must place an ultrathin insulating layer — known as a gate dielectric — on top of the semiconductor. Doing so on a 2D material is a little like laying a film over an exceptionally delicate sheet of paper: The process can easily damage or disrupt the surface underneath. Those imperfections scatter electrons as they move through the material, reducing speed and undermining device performance. The industry has therefore faced a persistent trade-off between making the insulating layer thinner and preserving efficient electron transport.


An Atomic-Scale Fix for the Interface Problem

Instead of searching for another semiconductor material, the research team redesigned the interface itself. Using a technique known as epitaxial interface engineering, the researchers deposited an ultrathin layer of aluminum directly onto monolayer MoS₂ under ultrahigh-vacuum conditions. They then carefully oxidized the aluminum to create an aluminum oxide layer measuring about 0.42 nanometers thick.

The atomically thin oxide forms a high-quality foundation for the growth of subsequent dielectric materials. It also improves the interface between the MoS₂ channel and the gate dielectric, helping electrons travel with less interference.

The resulting transistor combines an aggressively scaled dielectric structure with high transconductance — a measure of how effectively the gate voltage controls the device's current. Even at very small dimensions, the transistor demonstrated performance that ranks among the world’s leading MoS₂ devices, while maintaining extremely low leakage current and strong operational stability.

The results suggest that precise control of interfaces could help move 2D semiconductors beyond laboratory demonstrations and closer to real-world chip applications.

Building a Platform for the Post-Silicon Era

“The real competition in 2D semiconductors will not be about materials alone — it will be about interface engineering,” Chang said.

He said the broader value of the research lies in its potential to serve as a platform technology applicable to various 2D semiconductor materials. If successfully integrated with existing semiconductor manufacturing processes, the approach could support a new generation of faster, more energy-efficient electronic devices and help lay the groundwork for chip technologies in the post-silicon era.

The achievement also highlights Taiwan’s ability to connect government-backed research programs with academic expertise and industrial capabilities. With support from the NSTC, the collaboration combined the research strengths of NYCU and Academia Sinica with TSMC’s semiconductor expertise.

NYCU will continue advancing research in next-generation semiconductor materials and devices while strengthening partnerships with government agencies and industry, helping turn fundamental scientific discoveries into technologies with practical impact.
文圖/張文豪教授、國科會

手機、電腦，甚至未來的AI智慧裝置，都需要運算速度更快、耗電更低的半導體晶片。然而，傳統矽半導體技術，已逐漸逼近物理極限。為了解決這個問題，全世界的科學家都在尋找下一代的半導體材料，而「二維半導體」因為薄到只有原子級厚度，被視為延續摩爾定律，讓晶片持續微縮與提升效能的重要關鍵。
 
本校電子物理系、中研院應用科學研究中心張文豪教授團隊，攜手半導體工程學系李宗恩教授及台積電Iuliana Radu博士團隊，在國科會「Å世代前瞻半導體專案計畫」及「晶創臺灣-次世代半導體材料與元件整合關鍵技術」計畫支持下，針對二維半導體長期以來面臨的「介面問題」提出解決方案，成功開發出高效能的單層二硫化鉬(MoS2)頂閘極電晶體，這項突破性成果更登上國際頂尖期刊《Nature Electronics》。

「磊晶介面工程」突破二維半導體關鍵瓶頸

二維半導體雖有極致薄的優勢，但要讓它真正在晶片裡發揮作用，仍面臨一項關鍵挑戰：為了控制電流，必須在上面鋪一層超薄的「閘極介電層」。這就像要在超薄的紙上再鋪上一層膜，很容易在過程中破壞到紙張表面，這將導致電子傳輸受阻(電子散射)，使得元件效能受到嚴重影響。因此，如何兼顧超薄結構與高速電子傳輸，一直是國際半導體界難以跨越的高牆。
 


臺灣產學研團隊的創新之處，並不是去尋找另一種新材料，而是利用「磊晶介面工程」(epitaxial interface engineering)，重新設計了這層「膜」的結構。

研究團隊利用超高真空技術，先在單層MoS2表面精準鋪上一層超薄的鋁，再經氧化形成厚度僅約0.42奈米的氧化鋁層，作為後續材料生長的高品質基底。這個只有原子級厚度的完美介面，不僅大幅提升二維半導體與介電層之間的品質，更有效降低電子傳輸阻礙，成功兼顧「超薄」與「跨導」兩項關鍵特性。利用這項技術，團隊製作出的電晶體，在極小的尺寸下展現全球領先的跨導表現，同時具備極低漏電流與優異操作穩定性，展現二維半導體元件邁向實際應用的重要潛力。
 
介面工程奠定後矽時代科技基礎

張文豪教授表示，未來二維半導體真正的競爭，不只是材料，而是介面工程! 這項技術最大的價值，是建立可廣泛應用於不同二維半導體材料的平台技術。未來可望發展出更高速、更低功耗的電子元件，並與現有的半導體製程完美結合，為「後矽時代」的晶片技術奠定重要基礎，也再次展現臺灣在次世代半導體領域的創新實力與國際競爭力。

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